Hello. I've been poking around the schematics of the Colour Slab, and there's a bit of weirdness.
The address and data lines are multiplexed, meaning that all transfers down the data bus are 4 chunks of 8-bits ('040 reference, 7.11.2). For this to work, you need to reset the IC with the CDIS (cache disable) tied low. The CDIS pin is controlled by the bus controller on U37 (page 3 of schematics). Anyway, it's a multiplexed burst where address A1, A0 are cycled; however, what's fuzzy to me is if it's 8-bit or 32-bit aligned.
There seems to be some assumptions in the documentation which I haven't quite clued into. I cannot tell if NeXT did something very weird or very smart. Does anyone have any idea which case this might be?